HD74AC174 Datasheet, PDF (3/9 Pages) Hitachi Semiconductor – Hex D-Type Flip-Flop with Master Reset

Logic Diagram
HD74AC174
MR CP D5
D4
D3
D2
D1
D0
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
Q5
Q4
Q3
Q2
Q1
Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
Item
Symbol Max
Unit
Maximum quiescent supply current I_CC
80
µA
Maximum quiescent supply current I_CC
8.0
µA
Condition
V_IN = V_CC or ground, V_CC = 5.5 V,
Ta = Worst case
V_IN = V_CC or ground, V_CC = 5.5 V,
Ta = 25°C
AC Characteristics: HD74AC174
Item
Maximum clock
frequency
Symbol
f _max
V_CC (V)*¹
3.3
5.0
Ta = +25°C
C_L = 50 pF
Min Typ
90
100
100 125
Propagation delay
t _PLH
3.3
1.0
9.0
CP to Q_n
5.0
1.0
6.0
Propagation delay
t _PHL
3.3
1.0
8.5
CP to Q_n
5.0
1.0
6.0
Propagation delay
t _PHL
3.3
1.0
9.0
MR to Q_n
5.0
1.0
7.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Max
—
—
11.5
8.5
11.0
8.0
11.5
9.0
Ta = –40°C to +85°C
C_L = 50 pF
Min
Max
70
—
100
—
1.0
12.5
1.0
9.5
1.0
12.0
1.0
9.0
1.0
12.5
1.0
10.5
Unit
MHz
ns
ns
ns
3