HD151011 Datasheet, PDF (3/16 Pages) Hitachi Semiconductor – Dual BCD Programmable Counter with Synchronous Preset Enable

Pin Arrangement
HD151011
CO 1
J0 2
J1 3
J2 4
J3 5
J4 6
J5 7
J6 ₈
J7 9
GND 10
20 VCC
19 (Test 1)*
18 (Test 2)*
17 C / T
16 CLK
15 CLK
14 Q
13 PR
12 SPE
11 CLR
(Top view)
* Pins 18 and 19 are for function test only and should be open.
Pin Description
Pin Name
Input pins
J0 to J7
C/T
CLK, CLK
Output pins
SPE
PR
CLR
CO
Q
Pin Description
Count data input for option
Level change input for CLK, CLK (CMOS level or TTL level)
Clock inputs CLK : Rise edge trigger
CLK : Fall edge trigger
Preset input for Jn data
Preset input for D-type Flip Flop (Initialize "L" at Q output)
Clear input for D-type Flip Flop (Initialize "H" at Q output)
Output for BCD decimal counter
Output for D-type Flip Flop
3