HM538123B Datasheet, PDF (29/46 Pages) Hitachi Semiconductor – 1 M VRAM (128-kword x 8-bit)

Early Write Cycle
HM538123B Series
Note:
RAS
CAS
Address
WE
t _RC
t _RAS
tASR tRAH
Row
tWS tWH
*1
t _RCD
t _CSH
t _RSH
tCAS
tASC tCAH
Column
tWCS t_WCH
t _RP
t _CRP
I/O
(Output)
I/O
(Input)
DT/OE
DSF
tMS
tMH
Mask Data
tDTS tDTH
tFSR
tRFH
tDS
tDH
Valid Din
tFSC
tCFH
High-Z
1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
Delayed Write Cycle
Note:
RAS
CAS
Address
WE
t _RC
t _RAS
t _RCD
t _ASR
t _RAH
Row
t _WS t _WH
*1
t _ASC
Columun
t _CSH
t _RSH
t _CAS
t _CAH
t _RWL
t _WP
t _RP
t _CRP
t _CWL
I/O
(Output)
I/O
(Input)
t _MS
t _MH
Mask Data
t _DTS t _DTH
t _DZC
t _OFF2
t _ODD
t _DS t _DH
Valid Din
t _OEH
DT/OE
DSF
t _FSR t _RFH
t _FSC ^t CFH
1. This cycle becomes a normal mode write cycle when :( is high and a mask write cycle
when :( is low.
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