HD74HC195 Datasheet, PDF (2/9 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Register

HD74HC195
Function Table
Inputs
Shift/
Serial
Parallel
Outputs
Clear Load Clock J
K
A
B
C
D
Q_A
Q_B
Q_C
Q_D
Q_D
L
XX
X
X
X
X
X
X
L
L
L
L
H
H
L
X
X
a
b
c
d
a
b
c
d
d
H
H
L
X
X
X
X
X
X
Q_A0
Q_B0
Q_C0
Q_D0
Q_D0
H
H
L
H
X
X
X
X
Q_A0
Q_A0
Q_Bn
Q_Cn
Q_Cn
H
H
L
L
X
X
X
X
L
Q_An
Q_Bn
Q_Cn
Q_Cn
H
H
H
H
X
X
X
X
H
Q_An
Q_Bn
Q_Cn
Q_Cn
H
H
H
L
X
X
X
X
Q_An
Q_An
Q_Bn
Q_Cn
Q_Cn
H : high level (steady state)
L : low level (steady state)
X : don’t care
:
transition from low to high level.
a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively.
Q_A0, Q_B0, Q_C0, Q_D0 : the level of Q_A, Q_B, Q_C or Q_D respectively, before the indicated steady-state input
conditions were established.
Q_An, Q_Bn, Q_Cn, Q_Dn :
the level of Q_A, Q_B, Q_C or Q_D respectively before the most recent
the clock.
transition of
2