HD74AC393 Datasheet, PDF (2/10 Pages) Hitachi Semiconductor – Dual Modulo-16-Counter

HD74AC393
Logic Symbol (each half)
1, 13
CP
MR Q0 Q1 Q2 Q3
2, 12
4, 10
6, 8
3, 11
5, 9
Vcc=Pin14
GND=Pin7
Pin Names
CP
MR
Q₀ – Q₃
Clock Pulse Input (Active Falling Edge)
Asynchronous Master Reset Input (Active High)
Flip-flop Outputs
Functional Description
Each half of the HD74AC393 operates in the modulo-16 binary sequence, as indicated in the + 16 Truth
Table. The first flip-flop is triggered by High-to-Low transitions of the CP input signal. Each of the other
flip-flops is triggered by a High-to-Low transition of the Q output of the preceding flip-flop. Thus state
changes of the Q outputs do not occur simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding spikes and, therefore, should not be used as
clocks for other counters, registers or flip-flops. A High signal on MR forces all outputs to the Low state
and prevents counting.
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