HD74AC166 Datasheet, PDF (2/11 Pages) Hitachi Semiconductor – 8-bit Shift Register

HD74AC166/HD74ACT166
Logic Symbol
15 2 3 4 5 10 11 12 14
PE P0 P1 P2 P3 P4 P5 P6 P7
1
DS
7
6
1
2
CP
MR
Q7
9
13
VCC=Pin16
GND=Pin8
Pin Names
CP₁, CP₂
D_S
PE
P₀ to P₇
MR
Q₇
Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Parallel Enable Input (Active Low)
Parallel Data Inputs
Asynchronous Master Reset Input (Active Low)
Last Stage Output
Functional Description
Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of
either clock input if the other clock input is Low. When one of the clock inputs is used as an active High
clock inhibt, it should attain the High state while the other clock is still in the High state following the
previous operation. When the Parallel Enable (PE) input is Low, data is loaded into the register from the
Parallel Data (P₀ to P₇) inputs on the next rising edge of the clock. When PE is High, information is shifted
from the Serial Data (D_S) input to Q₀ and all data in the register is shifted one bit position (i.e., Q₀ → Q₁, Q₁
→ Q₂, etc.) on the rising edge of the clock.
2