HD151012 Datasheet, PDF (2/16 Pages) Hitachi Semiconductor – 8-bit Binary Programmable Counter with Synchronous Preset Enable

HD151012
Function Table
Control Inputs
CLR
PR
SPE
Mode
Operation Description
H
H
H
Generally count
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
X
X
L
Synchronous preset Jn data is preset at the rise of clock (CLK), the fall
of clock (CLK)
L
H
—
Initialize of Q output Initialize of Q = “L”
H
L
—
Initialize of Q output Initialize of Q = “H”
Notes: 1. Synchronous preset (SPE) input can set max 256 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
H : High level
L : Low level
X : Immaterial
— : Irrespective of condition
Pin Arrangement
J0 1
J1 2
J2 3
J3 4
J4 5
J5 6
J6 7
GND ₈
16 VCC
15 CLK
14 CLK
13 Q
12 _PR
11 SPE
10 CLR
9 J7
(Top view)
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