M61113FP Datasheet, PDF (13/17 Pages) Hitachi Semiconductor – Semiconductor integrated circuit built-in the PLL inter-carrier method VIF/SIF dedicated to NTSC.

M61113FP
Note 8 Inter Modulation: IM
• Input SG8 to VIF IN (Pin 16, 17), and measure video output TP1 with an oscilloscope.
• Adjust AGC filter voltage TP19 so that the minimum DC level of the output waveform is Vsync.
• At that time, measure TP1 with a spectrum analyzer. The inter modulation is defined as a difference between 0.92
MHz and 3.58 MHz frequency components.
Note 9 RF AGC Delay Point (TV Mode): RFDP
• Input SG12 to VIF IN (Pin 16, 17) and gradually reduce level and then measure the input level when RF AGC
output (TP14) reaches 1/2Vcc, as shown below.
• At that time, the state of Pin 7 is DC open.
TP14
Voltage
RFagcH
1/2Vcc
RFagcL
RFDP
SG12 Level
(dBµV)
Note 10 AFT sensitivity: µ, Maximum AFT Voltage: AFTH, Minimum AFT Voltage: AFTL
• Input SG13 to VIF IN (Pin 16, 17) and set the frequency of SG13 so that the voltage of AFT output TP13 is 3 volt.
The frequency is named f(3).
• Set the frequency of SG13 so that the AFT output voltage is 2 volt. This frequency is named f(2).
• In the graph shown below, maximum and minimum DC voltage are AFTH and AFTL, respectively.
µ=
1000 (mV)
f(2) - f(3) (KHz)
(mV/kHz)
TP13
Voltage
AFTH
3V
2V
AFTL
f (3)
f (2) f (MHz)
Rev.1.00, Aug.25.2003, page 13 of 16