SH7750 Datasheet, PDF (1/2 Pages) Hitachi Semiconductor – SuperH RISC Processor Product Brief

SuperH^TM RISC
PROCESSOR
TM
SH7750 (SH-4 Series)
SuperH^TM RISC Processor
Product Brief
Description
T he SH7750 (SH-4 series) is a high performance, cost-
effective, 2 issue superscalar RISC microprocessor
for embedded applications. The SuperH^TM architecture is
the leader in code density among RISC microprocessors,
reducing memory costs in embedded applications. It
features a 64-bit external data bus, a 16-bit fixed-length
instruction set and a 128-bit vector graphics engine.
T he SH7750 is used in consumer, computing, multi-
media, and communication markets. Applications
include handheld PCs, sub-notebook PCs, Internet
appliances, set top boxes, and game machines. The
device can be paired with an ASSP companion device
for a low cost, low IC count, and differentiated system.
Hitachi optimized the SH7750 MMU, cache size, and
peripheral mix for Windows^®CE applications.
Features
Hitachi SH-4 RISC Processor
• General
- 200 MHz/360 MIPS at 3.3V I/O, 1.8V internal
- 16 x 32-bit general purpose registers
- 256 pin LBGA
SH-4 Block Diagram
SH-4 CPU
• Two-way superscalar RISC
• 360 MIPs
• Upward compatible with SH-1/2/3
Integer Unit
32 bit
Floating Point Unit
64 bit
Cache
Instruction
8 KByte
Data
16 KByte
• WB/WT,
selectable
by page
Bus Unit
• Glueless interface to SDRAM,
EDO DRAM, fast page DRAM,
SRAM, and ROM
Data
bus
Memory Management Unit
• Full Windows CE support
• 1K/4K/64K/1MByte page sizes
Unified TLB
64 entry
Micro ITLB
4 entry
Specialized Math Circuits
• 3D floating point
acceleration hardware
Peripheral Functions
• DMA controller
• Programmable power management
• Interrupt controller
• Timers
• Real-time clock
• Serial interface
• User break controller
• 64/32/16/8 bits, 256-pin package
• CPU
- Code compatible with SH7000/7600/7700 series
- 16 x 32-bit general purpose registers
- 32 x 32-bit single-precision floating point registers
or 16 x 64-bit double-precision floating point registers
or 4 x 128-bit single-precision vector registers and
register matrix
- 16-bit fixed instruction length for high code density
- 32 x 32 + 64 --> 64 bits multiply-accumulate unit for
special functions such as software modems
- MMU Designed for Windows^®CE 1KB, 4KB, 64KB,
and 1MB page sizes, 64-entry, fully associative UTLB
- 4 entry, fully associative µITLB
- 5 stage pipeline
• Memory
- On-chip cache, 8KB instruction and 16KB data
• Write back or write through, selectable by page
• Low voltage cache to reduce power consumption
- On-chip bus state controller allows direct
connection to DRAM, SDRAM, SRAM, ROM, and
Flash ROM
• 8, 16, 32, or 64-bit data bus support
• Peripherals
- DMA, 4 channels
- Timers, 3 channels x 32-bits
- Watchdog timer