HM624100HC Datasheet, PDF (1/14 Pages) Hitachi Semiconductor – 4M High Speed SRAM (1-Mword x 4-bit)

HM624100HC Series
4M High Speed SRAM (1-Mword × 4-bit)
ADE-203-1198 (Z)
Preliminary
Rev. 0.0
Nov. 30, 2000
Description
The HM624100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed
access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The HM624100HC is packaged in 400-mil 32-pin SOJ for high
density surface mounting.
Features
• Single 5.0 V supply : 5.0 V ± 10 %
• Access time 10 ns (max)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
 All inputs and outputs
• Operating current : 140 mA (max)
• TTL standby current : 40 mA (max)
• CMOS standby ccurrent : 5 mA (max)
: 1.2 mA (max) (L-version)
• Data retension current : 0.8 mA (max) (L-version)
• Data retension voltage : 2.0 V (min) (L-version)
• Center V_CC and V_SS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.