HM62256B Datasheet, PDF (1/20 Pages) Hitachi Semiconductor – 256k SRAM (32-kword x 8-bit)

HM62256B Series
256k SRAM (32-kword × 8-bit)
ADE-203-135F (Z)
Rev. 6.0
Nov. 13, 1997
Description
The Hitachi HM62256B Series is a CMOS static RAM organized 32,768-word × 8-bit. It realizes higher
performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. The
device, packaged in 8 × 14 mm TSOP, 8 × 13.4 mm TSOP with thickness of 1.2 mm, 450 mil SOP (foot
print pitch width), 600 mil plastic DIP, or 300 mil plastic DIP, is available for high density mounting. It
offers low power standby power dissipation; therefore, it is suitable for battery backup systems.
Features
• Single 5.0 V supply: 5.0 V ± 10%
• Access time: 55 ns/70 ns/85 ns (max)
• Power dissipation:
 Active: 25 mW (typ) (f = 1 MHz)
 Standby: 1.0 µW (typ)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
 Three state output
• Directly TTL compatible all inputs and outputs
• Battery backup operation