HM530281R Datasheet, PDF (1/47 Pages) Hitachi Semiconductor – 331,776-word x 8-bit Frame Memory

HM530281R Series
331,776-word × 8-bit Frame Memory
ADE-203-251B
Rev. 1.0
June 6, 1997
Description
The HM530281R series memory products provide completely asynchronous I/O and operate at the high
speed of 50 MHz. The HM530281R series memory products provide reset, jump, and line increment/hold
pointer control functions that can be used in synchronization with independent clocks on each of the I/O
ports. Memory can be accessed immediately without any waiting period after the execution of these
functions. In addition to the FIFO function, the 281R series products support an address structure that is
compatible with HDTV, NTSC, and PAL standards, and can be used in a wide range of applications, such
as noise reducers, TBC (time-based correction), inter-frame YC separation, and special function modes
(e.g., multi-freeze, P-in-P) in the digital TV, VCR, and video camera application. They are also appropriate
for use as inter-system speed conversion buffer memories in communications systems, as cache memories
of HDD and MOD, and as frame buffer of VGA.
Features
• Organization: 331,776-word × 8-bit
• Completely asynchronous operation of the serial read port and write port.
 Internal generation of read and write addresses
 Internal memory operation control provided on-chip
• High speed read/write cycle time: 50 MHz
• Reset, jump functions
 Independent execution for read and write ports
 Can be executed with arbitrary timing
 Allow immediate access after execution (read/write) (for the jump function, when the address setup
is complete)
 Jump address specifiable in 32-word units
• 2 dimensional address
• Line increment/hold address pointer control function
• Window scan function