HD74LVC373A Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – Octal D-type Transparent Latches with 3-state Outputs

HD74LVC373A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-112B(Z)
3rd Edition
December 1996
Description
The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch
enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements. Low voltage and high speed operation is
suitable at the battery drive product (note type personal computer) and low power consumption extends the
life of a battery for long time operation.
Features
• V_CC = 2.0 V to 5.5 V
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_OUT (Max.) = 5.5 V (@V_CC = 0 V or output off state)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@V_CC = 3.0 V to 5.5 V)
Function Table
Inputs
G
LE
D
Output Q
H
X
X
Z
L
H
L
L
L
H
H
H
L
L
X
Q₀
H : High level
L : Low level
X : Immaterial
Z : High impedance
Q₀ : Level of Q before the indicated steady input conditions were established.