HD74LV138A Datasheet, PDF (1/13 Pages) Hitachi Semiconductor – 3-to-8 line Decoder / Demultiplexers

HD74LV138A
3-to-8 line Decoder / Demultiplexers
ADE-205-261 (Z)
1st Edition
March 1999
Description
The HD74LV138A is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. The conditions at the binary-select inputs and
the three enable inputs select one of eight input lines.
Two active-low and one active-high enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder
requires only one inverter.
An enable input can be used as a data input for demultiplexing applications.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• V_CC = 2.0 V to 5.5 V operation
• All inputs V_IH (Max.) = 5.5 V (@V_CC = 0 V to 5.5 V)
• All outputs V_O (Max.) = 5.5 V (@V_CC = 0 V)
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.3 V (@V_CC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@V_CC = 3.0 V to 3.6 V), ±12 mA (@V_CC = 4.5 V to 5.5 V)