HD74HCT74A Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – Dual D-type Positive Edge-triggered Flip Flops with Clear and Preset

HD74HCT74A
Dual D–type Positive Edge–triggered Flip Flops
with Clear and Preset
ADE-205-290 (Z)
1st. Edition
June 1999
Description
The HD74HCT74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin
package. The logic level present at the data input is transferred to the output during the positive going
transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level
at the appropriate input.
Features
• V_CC = 4.5 to 5.5 V operation
• Input terminal has protection diode
Function Table
Inputs
Outputs
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H ^*1
H ^*1
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q₀
Q₀
H : High level
L : Low level
X : Immaterial
↑ : Low to high transition
Q₀ : Level to Q before the indicated steady state input conditions were established.
Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if
preset and clear go high simultaneously.