HD74HCT125 Datasheet, PDF (1/9 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates (with 3-state outputs)

HD74HCT125/HD74HCT126
Quad. Bus Buffer Gates (with 3-state outputs)
Description
The HD74HCT125, HD74HCT126 require the 3-state control input C to be taken high to put the output
into the high impedance condition, whereas the HD74HCT125, HD74HCT126 requires the control input to
be low to put the output into high impedance.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: t_pd (A to Y) = 12 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: V_CC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
Function Table
Input
C
HCT125
HCT126
A
H
L
X
L
H
L
L
H
H
Notes: X: Irrelevant
Z: Off (High-impedance) state of a 3-state output.
Output Y
HD74HCT125
Z
L
H
HD74HCT126
Z
L
H