HD74HC95 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – 4-bit Parallel Access Shift Register

HD74HC95
4-bit Parallel Access Shift Register
Description
This 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs.
The register has three mode operation:
• Parallel (broadside) load
• Shift right (the direction Q_A toward Q_D)
• Shift left (the direction Q_D toward Q_A)
Parallel loading is accomplished by applying the four bits of data and taking the mode conrol input high.
The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of
the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the
high-to-low transition of clock-1 when the mode control is low; shift left is accomplished on the high-to-
low transition of clock-2 when the mode control is high by connecting the output of each flip-flop (Q_D to
input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock-1
and clock-2 if both modes can be clocked from the same source. Changes at the mode control input should
normally be made while both clock inputs are low: however, conditions described in the last three lines of
the function table will also ensure that register contents are protected.
Features
• High Speed Operation: t_pd (Clock to Q) = 17 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)