HD74HC595 Datasheet, PDF (1/10 Pages) Hitachi Semiconductor – 8-bit Shift Register/Latch (with 3-state outputs)

HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register and the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect
both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
Features
• High Speed Operation: t_pd (RCK to Q) = 17 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads (Q_A to Q_H outputs)
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
Function Table
RCK
X
X
X
SCK
X
X
X
SCLR G
X
H
L
X
H
X
H
X
Function
Q_A to Q_H high impedance
Shift register cleared Q_H’ = L
Shift register clocked Q_n = Q_{n – 1}, Q_A = SER
Contents of shift register transferred to output latches