HD74HC563 Datasheet, PDF (1/12 Pages) Hitachi Semiconductor – Octal Transparent Latches (with 3-state outputs)

HD74HC563/HD74HC573
Octal Transparent Latches (with 3-state outputs)
Description
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D
inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements.
Features
• High Speed Operation: t_pd (Data to Q, Q) = 11 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
Function Table
Outputs
Output Control Latch Enable
Data
HD74HC563
HD74HD573
L
H
H
L
H
L
H
L
H
L
L
L
H
X
X
Q₀
Q₀
X
Z
Z
Q₀ : level of Q before the indicated Steady-sate input conditions were established.
Q₀ : complement of Q₀ or level of Q before the indicated Steady-state input conditions were established.