HD74HC490 Datasheet, PDF (1/8 Pages) Hitachi Semiconductor – Dual 4-bit Decade Counters

HD74HC490
Dual 4-bit Decade Counters
Description
This circuit contains eight master-slave flip-flops and additional gating to implement two individual 4-bit
decade counters. Each decade counter has individual clock, clear and set-to-9 inputs. BCD count
sequences of any length up to divide-by-100 may be implemented with a single HD74HC490. Buffering
on each output is provided to ensure that suceptibility to collector communication is reduced significantly.
The counters have paralle outputs from each counter state so that submultiples of the input count frequency
are available for system timing signals.
Features
• High Speed Operation: t_pd (Clock to Q_A) = 13 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
Function Table
Clear/Set-To-9
Inputs
Outputs
Clear
Set-To-9
Q_A
Q_B
Q_C
Q_D
H
L
L
L
L
L
L
H
H
L
L
H
L
L
Count