HD74HC279 Datasheet, PDF (1/9 Pages) Hitachi Semiconductor – Quad. S-R Latches

HD74HC279
Quad. S–R Latches
Description
The latch is ideally suited for use as temporary stage for binary information processing and input/output
units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is
stored before the indicated steady-state input conditions were established. And when both inputs are low,
output is high, but this high level are uncontinuance, if either of input goes high.
Features
• High Speed Operation: t_pd (S to Q) = 10 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 2 µA max (Ta = 25°C)
Function Table
Input
Output
S*²
R
Q
H
H
Q₀
L
H
H
H
L
L
L
L
H*¹
H : High level
L : Low level
Q₀ : The level of Q respectively, before the indicated steady-state input conditions were established.
Notes: 1. It is unpredictable, if S or R goes High.
2. As to latches which has two S inputs.
H: Both of S inputs are high.
L: Either or both of S inputs are low.