HD74HC165 Datasheet, PDF (1/9 Pages) Hitachi Semiconductor – Parallel-load 8-bit Shift Register

HD74HC165
Parallel-load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from Q_A to Q_H when clocked. Parallel inputs to each stage are
enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
• High Speed Operation: t_pd (Clock to Q_H) = 21 ns typ (C_L = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: V_CC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: I_CC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Shift/Load
L
H
H
H
H
Clock Inhibit
X
L
L
L
H
Clock
X
L
X
Parallel
Serial A ······ H
X
a ······h
X
X
H
X
L
X
X
X
Internal outputs
Q_A
Q_B
a
b
Q_A0
H
Q_B0
Q_An
L
Q_An
Q_A0
Q_B0
Output
Q_H
h
Q_H0
Q_Gn
Q_Gn
Q_H0