HD74ALVCH162835 Datasheet, PDF (1/13 Pages) Hitachi Semiconductor – 18-bit Universal Bus Drivers with 3-state Outputs

HD74ALVCH162835
18-bit Universal Bus Drivers with 3-state Outputs
ADE-205-189B (Z)
3rd. Edition
December 1999
Description
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent
mode when LE is high. The A data is latched if CLK is held at a high or low logic level. If LE is low, the
A bus data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the
outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating
data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω
resistors to reduce overshoot and undershoot.
Features
• V_CC = 2.3 V to 3.6 V
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@V_CC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.