HD74ALVC162834A Datasheet, PDF (1/16 Pages) Hitachi Semiconductor – 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable

HD74ALVC162834A
18-bit Universal Bus Driver with 3-state Outputs
and Inverted Latch Enable
ADE-205-293A (Z)
2nd. Edition
November 1999
Description
The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V_CC operation.
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode
when the latch enable (LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If the LE is high, the A data is stored in the latch/flip flop on the low to high
transition of CLK. When OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down, OE should be tied to V_CC through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include series dumping resistors to reduce overshoot
and undershoot.
Features
• Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
• V_CC = 2.3 V to 3.6 V
• Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
• Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@V_CC = 3.0 V)
• All outputs have series dumping resistors, so no external resistors are required
• t_pd (CLK to Y) = 3.5 ns (Max) (@V_CC = 3.3±0.3 V, C_L = 50 pF, Ta = 0 to 85°C)
• t_pd (CLK to Y) = 2.5 ns (Max) (@V_CC = 3.3±0.3 V, C_L = 30 pF, Ta = 0 to 85°C)