LXT381II Datasheet, PDF (1/36 Pages) Intel Corporation – Octal E1 Line Interface Unit

LXT381
Octal E1 Line Interface Unit
Datasheet
General Description
The LXT381 is an octal short haul analog Line Interface Unit for ITU G.703 2.048 Mbit/sec.
transmission systems. It incorporates eight independent receivers and eight independent
transmitters in a single LQFP-144 or PBGA-160 package.
The transmit output drivers provide low impedance, constant during marks and spaces and
constant pulse amplitudes independent of supply voltage variations.
The LXT381 may be configured for unbalanced 75Ω or for balanced 120Ω systems without
external component changes in the transmit section. The transmit return loss performance
exceeds latest ETSI return loss recommendations such as ETS 300166.
The LXT381 features a differential data receiver architecture with high noise interference
margin. The receivers use peak detection and a variable threshold for reliable data recovery
down to 500 mV or up to 12 dB of cable attenuation.
Each receiver incorporates an analog Loss Of Signal (LOS) processor that meets latest ITU
G.775 standard.
The fast power down mode of all transmitters allows the implementation of Hitless Protection
Switching (HPS) application without the use of relays.
Applications
s Synchronous Digital Hierarchy (SDH) E1 tributary interfaces
s Public switching trunk line interfaces
s Digital Access Cross Connects (DACS)
s Microwave transmission systems
Product Features
s Octal E1 short haul line interface per ITU
G.703
s Single rail supply voltage of 3.3V with 5V
I/O capability
s Low power consumption of <100 mW per
channel (typ.)
s 75Ω/120Ω TX operation without
component changes
s Transmit return loss complies with ETSI
ETS 300 166
s Hitless Protection Switching (HPS)
s Driver short circuit current limiter (<50 mA
RMS)
s Differential receiver with 15dB of signal to
noise interference margin
s Data recovery with no need for external
reference clock
s Analog LOS detection per ITU G.775
s Simple hardware control mode
s JTAG Boundary Scan test port per IEEE
1149.4
s Small footprint 144 pin LQFP or 160 pin
PBGA package
As of January 15, 2001, this document replaces the Level One document
known as Octal E1 Line Interface.
Order Number: 249005-001
January 2001