ATM12864D Datasheet, PDF (17/21 Pages) HB Electronic Components – Liquid Crystal Display Module

E
R/W
CS1B,CS2B
CS3,RS
DB0~DB7
64CH Segment Driver For Dot Matrix LCD 16
t_C
t_WL
t_WH
tR
tF
t_ASU
t_AH
t_ASU
t_AH
t_D
t_WH
MPU Read timing
OPERATING PRINCIPLES & METHODS
1. I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to
CS3 is in active mode, Input or output of data and instruction does not execute. Therefore
internal state is not change. But RSTB and ADC can operate regardless CS!B-CS3.
2. Input register
Input register is provided to interface with MPU which is different operating frequency. Input
register stores the data temporarily before writing it into display RAM.
When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data
from MPU is written into input register. Then writing it into display RAM. Data latched for falling
of the E signal and write automatically into the display data RAM by internal operation.
3. Output register
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3
are in active mode and R/W and RS=H, stored data in display data RAM is latched in output
register. When CS1B to CS3 is in active mode and R/W=H , RS=L, status data (busy check)
can read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first
access, data in display data RAM is latched into output register. In second access, MPU can
read data which is latched. That is to read the data in display data RAM, it needs dummy read.
But status read is not needed dummy read.