CD74HC373 Datasheet, PDF (8/8 Pages) Texas Instruments – High Speed CMOS Logic Octal Transparent Latch, Three-State Output

CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Test Circuits and Waveforms (Continued)
6ns
OUTPUT
DISABLE
50%
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
t_PLZ
t_PHZ
90%
10%
90%
6ns
10%
t_PZL
t_PZH
V_CC
GND
50%
50%
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
t_r
6ns
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
t_f
2.7
1.3
6ns
0.3
t_PZL
3V
GND
10%
90%
t_PZH
OUTPUTS
DISABLED
1.3V
1.3V
OUTPUTS
ENABLED
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREE-
STATE
OUTPUT
OUTPUT
R_L = 1kΩ
C_L
50pF
V_CC FOR t_PLZ AND t_PZL
GND FOR t_PHZ AND t_PZH
NOTE: Open drain waveforms t_PLZ and t_PZL are the same as those for three-state shown on the left. The test circuit is Output R_L = 1kΩ to
V_CC, C_L = 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
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