CA3126 Datasheet, PDF (7/9 Pages) Intersil Corporation – TV Chroma Processor

CA3126
Application Information
Circuit Description (Pin numbers refer to the DIP package.)
The following paragraphs briefly describe the circuit operation
of the CA3126 (shown in the Block Diagram and Schematic
Diagram). A detailed description of the operation of various
portions of the CA3126 is given in AN6247, “Application of the
CA3126 Chroma-Processing lC Using Sample-and-Hold
Techniques”.
The chroma input is applied to Terminal 1 through the desired
band-shaping network. A 2,450Ω resistor should be placed in
series with Terminal 1 to minimize oscillator pickup in the first
chroma amplifier. This amplifier supplies signals to the second
chroma amplifier and to the ACC and AFPC detectors. The
first chroma amplifier is gain-controlled by the ACC amplifier.
A horizontal keying pulse is applied to Terminal 9. This pulse
must be present to ensure proper operation of the oscillator cir-
cuit. The subcarrier burst is sampled during the keying interval
in the AFPC detector. The error voltage, produced at Terminal 2
and proportional to the burst phase, is compared to the quies-
cent bias voltage at Terminal 3 by the sample-and-hold circuitry.
This “compared” voltage controls the phase- shifting network in
the phase-locked loop. The operation of the AFPC loop is inde-
pendent of any external adjustments or voltages except for an
initial capacitor adjustment to set the free-running frequency.
The regenerated oscillator signal at Terminal 8 is applied
internally to the AFPC and ACC detectors through +45 and
-45-degree phase-shifter networks to establish the proper
phase relationship for these detectors. The ACC detector,
which also samples the burst during the keying interval, pro-
duces a correction voltage proportional to the burst ampli-
tude. The correction voltage is compared to the quiescent
bias level using sample-and-hold circuitry similar to that
used in the AFPC portion of the circuit. The “compared” volt-
age is applied internally to the ACC amplifier and killer
amplifier. Because the amplifier gains and killer threshold
are determined by the ratios of the internal resistors, these
functions are independent of external voltages or controls.
The attenuated chroma signal is fed to the second chroma
amplifier, where the burst is removed by keyer action. The
killer amplifier, the chroma gain control, and the overload
detector control the action of the second chroma amplifier,
whose gain is proportional to the dc voltage at Terminal 16.
The overload detector (Terminal 13) receives a sample of
the chroma output (Terminal 15) and detects the peak of the
signal. The detected voltage is stored in an external capaci-
tor connected to Terminal 16. This stored voltage on Termi-
nal 16 affects the gain of the second chroma in the same
manner as the chroma gain control.
General Considerations
The block diagram shown is typical of the type of circuit used
in the practical application of the CA3126. Several items are
critical for proper operation of the circuit.
1. A series resistor of approximately 2,450Ω (or high source
impedance) must be used at the chroma input, Terminal
1. This high impedance minimizes pickup of unbalanced
currents, particularly of the subcarrier oscillator signal.
2. When the overload detector is used, a large resistor
(nominally 47,000Ω) must be placed in series with Termi-
nal 16 to set the required RC time constant. The same
RC network series serves to set the killer time constant.
3. The setting of the free-running oscillator frequency
requires the presence of the keying pulse. The free-run-
ning frequency will be erroneous if Terminal 1 is DC
shorted during the setting operation because of the DC
offset voltage introduced to the AFPC detector.
4. Care must be taken in PC board designs to provide reason-
able isolation between the oscillator portion of the circuit
(Terminals 6, 7, and 8) and the chroma input (Terminal 1).
Overload Detector
The overload detector accomplishes two purposes:
1. It prevents oversaturation due to low burst-to-chroma ratios.
2. It prevents overload conditions due to noise.
Both of these conditions are discussed in more detail in
AN6247. The extent to which the overload detector is used
depends upon the individual receiver design goals. If greater
than 0.5V_P-P output is desired, the chroma output at Termi-
nal 15 can be tapped to yield any desired degree of overload
detector action.
Chroma Gain Control
The chroma gain control operates by varying the base bias on
current source transistor Q₂₅. To ensure proper temperature
tracking of the chroma gain control, it is essential that the con-
trol be operated from a supply source derived from the refer-
ence voltage at Terminal 12. Because the control operates from
a current source, chroma gain is much more predictable and far
less temperature sensitive than controls that steer current by
means of a differential amplifier. The typical chroma gain char-
acteristic for the CA3126 is shown in Figure 1.
T_A = 25^oC, CHROMA INPUT = 0.5V_P-P
100
80
60
40
20
0
20
40
60
80
100 120
140
VOLTAGE AT TERMINAL 16 (% OF V₁₂)
FIGURE 1. CHROMA GAIN CONTROL
Subcarrier Regenerator Oscillator
The oscillator filter consists of a 3.579545MHz crystal, a 680Ω
resistor, and a 10pF capacitor connected in series across Ter-
minals 6 and 7. A 33pF capacitor, shunt connected from Termi-
nal 7 to ground, rolls off higher order harmonics, thereby
preventing oscillation at the crystal third-harmonic frequency. A
8-39