HSD64M64F8K Datasheet, PDF (8/12 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on 32Mx8, 4Banks, 4K Ref., 3.3V

HANBit
HSD64M64F8K
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
PARAMETER
-1H
SYMBOL
MIN
MAX
CLK cycle time CAS latency=3
t_CC
CAS latency=2
10
1000
10
CLK to valid
CAS latency=3
6
t_SAC
output delay
CAS latency=2
6
Output data
CAS latency=3
3
t_OH
hold time
CAS latency=2
3
CLK high pulse width
t_CH
3
CLK low pulse width
t_CL
3
Input setup time
t_SS
2
Input hold time
t_SH
1
CLK to output in Low-Z
t_SLZ
1
CLK to output CAS latency=3
6
t_SHZ
in Hi-Z
CAS latency=2
6
-1L
MIN MAX
10
1000
12
6
7
3
3
3
3
2
1
1
6
7
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
1
1,2
1,2
3
3
3
3
2
1
1
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 8-
HANBit Electronics Co.,Ltd.