HMN88D Datasheet, PDF (8/9 Pages) Hanbit Electronics Co.,Ltd – Non-Volatile SRAM MODULE 64Kbit (8K x 8-Bit),28Pin DIP, 5V

HANBit
HMN88D
- WRITE CYCLE NO.2 (/CE-Controlled)^*1,2,3,4,5
tWC
Address
tAW
tAS
tCW
tWR2
/CE
/WE
DIN
DOUT
tWP
tWZ
Data Undefined (2)
tDW
tDH2
Data-in Valid
High-Z
NOTE: 1. /CE or /WE must be high during address transition.
2. Because I/O may be active (/OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
3. If /OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
- POWER-DOWN/POWER-UP TIMING
tPF
VCC
4.75
VPFD
4.25
VSO
VPFD
VSO
tFS
tWPT
tDR
tPU
tCER
/CE
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
8
HANBit Electronics Co.,Ltd