HDD128M72D18RPW Datasheet, PDF (8/14 Pages) Hanbit Electronics Co.,Ltd – DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register

HANBit
Address and Control Input hold time(Slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate(x16)
Output Slew Rate Matching Ratio(rise to fall)
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
HDD128M72D18RPW
tIH
tHZ
t LZ
t SL(IO)
t SL(O)
t SL(O)
t SL(O)
t SLMR
tMRD
tDS
tDH
tIPW
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
0.8
-0.7
-0.7
0.5
0.5
1.0
0.7
0.67
12
0.45
0.45
2.2
1.75
6
75
200
7.8
tHP
-tQHS
tCLmin or
tCHmin
0.4
+0.7
+0.7
4.5
5
1.5
-
-
0.55
0.6
1.0
-0.75
-0.75
0.5
0.5
1.0
0.7
0.67
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
tHP
-tQHS
tCLmin or
tCHmin
0.4
+0.75
+0.75
4.5
5
1.5
-
-
0.75
0.6
1.0
-0.75
-0.75
0.5
0.5
1.0
0.7
0.67
15
0.5
0.5
2.2
1.75
7.5
75
200
7.8
tHP
-tQHS
tCLmin or
tCHmin
0.4
+0.75
+0.75
4.5
5
1.5
-
-
0.75
0.6
tRAP
18
20
20
(tWR/tCK)+
tDAL
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
ns i, 6~9
ns
1
ns
1
ns
tCK
tCK
ns
ns
j, k
ns
j, k
ns
8
ns
8
ns
ns
tCK
ns
4
ns
11
ns 10,11
ns
11
tCK
2
tCK
13
Notes :
Maximum burst refresh of 8.
tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving.
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low)
applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time,
depending on tDQSS.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
URL : www.hbe.co.kr
REV 1.0 (January. 2005)
8
HANBit Electronics Co.,Ltd.