HSD64M64B8W Datasheet, PDF (7/10 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 512Mbyte(64Mx64-Bit), 144pin SO-DIMM, 4Banks, 8K Ref., 3.3V

HANBit
HSD64M64B8W
3.3V
D_OUT
870Ω
1200Ω
50pF*
D_OUT
V_OH (DC) = 2.4V, I_OH = -2mA
V_OL (DC) = 0.4V, I_OL = 2mA
(Fig. 1) DC output load
V_tt=1.4V
Z0=50Ω
50Ω
50pF
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
t_RRD(min)
t_RP(min)
t_RP(min)
t_RAS(min)
t_RAS(max)
Row cycle time
tRC^(min)
Last data in to row precharge
t_RDL(min)
Last data in to Active delay
t_DAL(min)
Last data in to new col. address delay
t_CDL(min)
Last data in to burst stop
t_BDL(min)
Col. address to col. address delay
t_CCD(min)
Number of valid output data
CAS latency=3
CAS latency=2
VERSION
-13
-10
-10L
15
20
20
20
20
20
20
20
20
45
50
50
UNIT NOTE
ns
1
ns
1
ns
1
ns
1
100
ns
65
70
70
ns
1
2
CLK
2.5
2 CLK + 20 ns
1
CLK
2
1
CLK
2
1
CLK
3
2
-
1
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.
URL : www.hbe.co.kr
Rev.1.0 (August / 2002)
7
HANBit Electronics Co.,Ltd.