HMS25632M8B Datasheet, PDF (7/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 1Mbyte (256K x 32-Bit) , 72-Pin

HANBit
HMS25632M8B/Z8B
TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed )
t_WC
Address
/CE
/WE
t_AS(4)
t_AW
t_CW(3)
t_WP(2)
t_WR(5)
t_OH
Data In
Data Out
High-Z
t_WHZ(6,7)
t_DW
t_DH
t_OW
High-Z(8)
(10)
(9)
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low : A write ends at the earliest transition among /CE going high and /WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
H
X*
L
H
L
H
L
L
Note: X means Don't Care
/OE
MODE
I/O PIN
SUPPLY CURRENT
X
Not Select
High-Z
l _SB, l _SB1
H
Output Disable
High-Z
l_CC
L
Read
D_OUT
l_CC
X
Write
D_IN
l_CC
7
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