HMS1M32M8G Datasheet, PDF (7/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 4Mbyte(1M x 32-Bit)

HANBit
HMS1M32M8G/Z8
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
t_WP is measured from the beginning of write to the end of write.
3. t_CW is measured from the later of /CE going low to the end of write.
4. t_AS is measured from the address valid to the beginning of wirte.
5. t_WR is measured from the end of write to the address change. t_WR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. D_OUT is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
/OE
MODE
H
X*
X
Not Select
L
H
H
Output Disable
L
H
L
Read
L
L
X
Write
Note: X means Don't Care
I/O PIN
High-Z
High-Z
D_OUT
D_IN
SUPPLY CURRENT
I _SB, I _SB1
I_CC
I_CC
I_CC
7
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