HMS12832M4 Datasheet, PDF (6/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 512KByte (128K x 32-Bit)

HANBit
HMS12832M4
TIMING WAVEFORM OF READ CYCLE ( /CE Controlled )
t_RC
Address
/CE
/OE
Data Out
Vcc Supply
Current
High-Z
l_CC
l_SB
t_AA
t_CO
t_LZ(4,5)
t_OE
t_OLZ
t_PU
50%
Data Valid
t_HZ(3,4,5)
t_OHZ
t_OH
t_PD
50%
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CE = VIL.
7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE=Clock )
Address
/OE
/CE
/WE
Data In
Data Out
t_AS(4)
t_WC
t_AW
t_CW(3)
t_WP(2)
High-Z
t_OHZ(6)
t_WR(5)
t_DW
t_DH
Data Valid
t_OW
High-Z
6
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