HDD16M72D9RPW Datasheet, PDF (6/10 Pages) Hanbit Electronics Co.,Ltd – DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register

HANBit
HDD16M72D9RPW
INPUT/OUTPUT Capacitance (V_DD = 2.5V, V_DDQ = 2.5V, T_A = 25° C, F = 1MHZ)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE )
Input Capacitance(CKE0)
Input Capacitance( CS0)
Input Capacitance( CLK0, CLK1,CLK2 )
Data & DQS input/output Capacitance(DQ0~DQ63)
Input Capacitance(DM0~DM8)
C_IN1
49
C_IN2
42
C_IN3
42
C_IN4
22
C_OUT1
6
C_IN5
6
57
pF
50
pF
50
pF
25
pF
8
pF
8
pF
AC Operating Conditions
PARAMETER/ Condition
STMBOL
MIN
MAX
UNIT NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals V_IH (AC) V_REF + 0.31
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. V_IL (AC)
V_REF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
V_ID (AC)
0.7
V_DDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
V_IX (AC) 0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
V
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation.
the AC and DC input specificatims are refation to a VREF envelope that has been bandwidth limited 20MHz.
AC Operating TEST Conditions
PARAMETER
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(V_IH/V_IL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
VALUE
0.5 * V_DDQ
1.5
0.5
V_REF+0.31/V_REF-0.31
V_REF
V_TT
See Load Circuit
UNIT
V
V
V/ns
V
V
V
V
NOTE
URL : www.hbe.co.kr
REV 1.0 (November.2002)
6
HANBit Electronics Co.,Ltd.