HFDOM44S3VXXX Datasheet, PDF (5/29 Pages) Hanbit Electronics Co.,Ltd – 44Pin Flash Disk Module Min.16MB ~ Max.384MB, True IDE Interface

HANBit
HFDOM44S3Vxxx
Signal Descriptions
Table 2.2 Signal Descriptions
Signal Name Dir.
Pin
Description
A[2:0]
-PDIAG
-DASP
-CS0, -CS1
D[15:00]
GND
-IOR
-IOW
IRQ
-RESET
In True IDE Mode only A[2:0] are used to select the one of eight registers in
I
33,35,36 _{the Task File, the remaining address lines should be grounded by the host.}
This input / output is the Pass Diagnostic signal in the Master / Slave
I/O
34 _{handshake protocol.}
In the True IDE Mode, this input/output is the Disk Active/Slave
I/O
39 _{Present signal in the Master/Slave handshake protocol.}
CS0 is the chip select for the task file registers while CS2 is used to select
I
37,38 _{the Alternate Status Register and the Device Control Register.}
3,4,5,6,
All Task File operations occur in byte mode on the low order bus D00-D07
while all data transfers are 16 bit using D00-D15.
7,8,9,10,
I/O 11,12,13,
14,15,16,
17,18
2,19,22, ^Ground.
--
24,26,
30,40,43
I
25 ^{This is an I/O Read strobe generated by the host.}
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
into the Storage Card controller registers when the Storage Card is
I
23 _{configured to use the I/O interface. The clocking will occur on the negative to}
positive edge of the signal (trailing edge).
O
31
In True IDE Mode signal is the active high Interrupt Request to the host.
I
1
This input pin is the active low hardware reset from the host.
IORDY
-IOIS16
VCC
O
O
Power
27
32
41,42
This output signal may be used as IORDY.
This output signal is asserted low when this device is expecting a word data
transfer cycle.
Power
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Rev. 1.0 (January, 2005)
5 / 29
HANBit Electronics Co., Ltd.