HMN12816D Datasheet, PDF (2/9 Pages) List of Unclassifed Manufacturers – Non-Volatile SRAM MODULE 2Mbit (128K x 16-Bit), 40pin-Dip, 5V

HANBit
HMN12816D
FUNCTIONAL DESCRIPTION
The HMN12816D devices execute a read cycle whenever /WE (Write Enable) is inactive (high) and either/both of /CEU or
/CEL (Chip Enables) are active (low) and /OE (Output Enable) is active (low). The unique address specified by the 17
address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The status of /CEU and /CEL
determines whether all or part of the addressed word is accessed. If /CEU is active with /CEL inactive, then only the upper
byte of the addressed word is accessed. If /CEU is inactive with /CEL active, then only the lower byte of the addressed
word is accessed. If both the /CEU and /CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will
be available to the 16 data output drivers within t_ACC (Access Time) after the last address input signal is stable, providing
that /CEU, /CEL and /OE access times are also satisfied. If /CEU, /CEL, and /OE access times are not satisfied, then data
access must be measured from the later occurring signal, and the limiting parameter is either t_CO for /CEU, /CEL, or t_OE for
/OE rather than address access.
The HMN12816D devices execute a write cycle whenever /WE and either/both of /CEU or /CEL are active (low) after
address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines which of the 131,072
words of data is accessed. The status of /CEU and /CEL determines whether all or part of the addressed word is
accessed. If /CEU is active with /CEL inactive, then only the upper byte of the addressed word is accessed. If /CEU is
inactive with /CEL active, then only the lower byte of the addressed word is accessed. If both the /CEU and /CEL inputs
are active (low), then the entire 16-bit word is accessed. The write cycle is terminated by the earlier rising edge of /CEU
and/or /CEL, or WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for
a minimum recovery time (t_WR ) before another cycle can be initiated. The /OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (/CEU and/or /CEL, and /OE active)
then /WE will disable the outputs in t_ODW from its falling edge.
PIN DESCRIPTION
A₀-A₁₆ : Address Inputs
/CEU : Chip enable upper byte
/CEL : Chip enable lower byte
DQ₀-DQ₁₅ : Data input / Data output
/WE : Write enable
/OE : Output enable
V_CC : +5V power supply
V_ss : Ground
BLOCK DIAGRAM
/OE
/WE
/CEL
/CEU
2 x 128K x 8
SRAM
Block
A0-A16
DQ0-DQ15
Power /CEL
/CEU
Power – Fail
VCC
Control
Lithium
Cell
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
2
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