HSD128M72B9K Datasheet, PDF (1/11 Pages) Hanbit Electronics Co.,Ltd – Synchronous DRAM Module 1024Mbyte (128Mx72Bit), 8K Ref., 3.3V ECC Unbuffered SO-DIMM,

HANBit
HSD128M72B9K
Synchronous DRAM Module 1024Mbyte (128Mx72Bit), 8K Ref., 3.3V
ECC Unbuffered SO-DIMM,
Part No. HSD128M72B9K
GENERAL DESCRIPTION
The HSD128M72B9K is a 128M x 72 bit Synchronous Dynamic RAM high density memory module. The module
consists of nine CMOS 128M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-
epoxy substrate. One or two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each
SDRAM. The HSD128M72B9K is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting
into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications All module components
may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
• JEDEC standard 3.3V power supply
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible with multiplexed address
• Separate power and ground planes to improve immunity
• Height : 1.250 inches
• MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 16M x 8bit x 4Banks Synchronous DRAM
• Part Identification
HSD128M72B9K-F/10L : 100MHz (CL=3)
HSD128M72B9K-F/10 : 100MHz (CL=2)
HSD128M72B9K-F/12 : 125MHz (CL=3)
HSD128M72B9K-F/13 : 133MHz (CL=3)
** F means Auto & Self refresh with Low-Power (3.3V)
URL : www.hbe.co.kr
REV.0.0(January. 2003)
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HANBit Electronics Co.,Ltd.