S7986-01_09 Datasheet, PDF (6/8 Pages) Hamamatsu Corporation – CCD area image sensor Back-thinned FT-CCD for low-light-level NTSC B/W TV application

s Dimensional outlines (unit: mm)
S7986-01
Window 12.0*
Active area 6.860
24
13
CCD area image sensor S7986-01, S7987-01
S7987-01
Window 12.0*
Active area 6.860
24
13
1
Index mark
1st pin index mark
12
2.54 ± 0.13
44.0 ± 0.44
Photosensitive surface
o (24 ×) 0.5 ± 0.05
Index mark
1
12
2.54 ± 0.13
44.0 ± 0.44
52.0
60.0 ± 0.3
1st pin index mark
Photosensitive surface
* Size of window that guarantees the transmittance in the
“Spectral transmittance characteristics of window material” graph.
o (24 ×) 0.5 ± 0.05
KMPDA0103EB
* Size of window that guarantees the transmittance in the
“Spectral transmittance characteristics of window material” graph.
KMPDA0104EB
s Pin connections
Pin
S7986-01
S7987-01
no. Symbol
Function
Symbol
Function
1
RD Reset drain
RD Reset drain
2
OS Output transistor source
OS Output transistor source
3
OD Output transistor drain
OD Output transistor drain
4
OG Output gate
OG Output gate
5
SG Summing gate
SG Summing gate
6
-
-
7
-
-
8
P2H CCD horizontal register clock-2
P2H CCD horizontal register clock-2
9
P1H CCD horizontal register clock-1
P1H CCD horizontal register clock-1
10 IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2)
11 IG1H Test point (horizontal input gate-1) IG1H Test point (horizontal input gate-1)
12
ISH Test point (horizontal input source) ISH Test point (horizontal input source)
13
TG Transfer gate
TG Transfer gate
14
P2VS
CCD vertical register clock-2
(storage area)
P2VS
CCD vertical register clock-2
(storage area)
15
P1VS
CCD vertical register clock-1
(storage area)
P1VS
CCD vertical register clock-1
(storage area)
16
-
Th1 Thermistor
17
-
Th2 Thermistor
18
-
P- TE-cooler-
19
-
P+ TE-cooler+
20
SS Substrate (GND)
SS Substrate (GND)
21
P2VI
CCD vertical register clock-2
(image area)
P2VI
CCD vertical register clock-2
(image area)
22
P1VI
CCD vertical register clock-1
(image area)
P1VI
CCD vertical register clock-1
(image area)
23
-
-
24
RG Reset gate
RG Reset gate
*15: TG is an isolation gate between vertical register and horizontal resister.
In standard operation, the same pulse of P2VS should be applied to the TG.
Remark
(standard operation)
+12 V
RL=2.2 kΩ
+15 V
+3 V
Same timing as P2H
-8 V
-8 V
Shorted to RD
Same timing as P2VS*¹⁵
GND
6