S10227-10_15 Datasheet, PDF (3/7 Pages) Hamamatsu Corporation – CMOS linear image sensor

CMOS linear image sensor
S10227-10
Timing chart
chart (S9227-03)
CLK
1/f(CLK)
Trigger
1 2 3 4 5 6 7 8 9 101112 131415
2.5 clocks
Integration time
8.5 clocks
ST
Video
EOS
thp(ST)
tpi(ST)
tlp(ST)
100 ns
512
14 clocks
tf(CLK)
tr(CLK)
CLK
1/f(CLK)
ST
tr(ST)
tf(ST)
thp(ST)
tpi(ST)
tlp(ST)
CLK
Video
tvd1
tvd2
KMPDC0166E
KMPDC0166EF
Parameter
Symbol
Min.
Typ.
Max.
Unit
Start pulse interval
Start pulse high period
tpi(ST)
530/f(CLK)
-
thp(ST)
8/f(CLK)
-
1100 m
s
1000 m
s
Start pulse low period
tlp(ST)
15/f(CLK)
-
100 m
s
Start pulse rise and fall times
tr(ST), tf(ST)
0
20
30
ns
Clock pulse duty
-
45
50
55
%
Clock pulse rise and fall times
tr(CLK), tf(CLK)
0
20
30
ns
Video delay time 1
Video delay time 2
tvd1
32
40
48
ns
tvd2
40
50
60
ns
Note: Dark output increases if the start pulse period or the start pulse high period is lengthened.
The internal timing circuit starts operating at the rise of CLK pulse immediately after ST pulse sets to low.
The integration time equals the high period of ST pulse plus 6 CLK cycles.
The output from 1st channel appears 14 clocks plus 100 ns after the falling edge of ST pulse.
The EOS pulse is output 39 ns after the falling edge of CLK pulse.
The output voltage after reading the last pixel (512 ch) is indefinite.
Start pulse setting example (for setting the start pulse period to a minimum and the integration time to a maximum)
Start pulse high period=515/f(CLK), Start pulse low period=15/f(CLK)
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