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G12460-0606S_15 Datasheet, PDF (1/9 Pages) Hamamatsu Corporation – Image sensor with 64 x 64 pixels developed for two-dimensional infrared imaging
InGaAs area image sensor
G12460-0606S
Image sensor with 64 × 64 pixels developed
for two-dimensional infrared imaging
The G12460-0606S has a hybrid structure consisting of a CMOS readout circuit (ROIC: readout integrated circuit) and back-
illuminated InGaAs photodiodes. Each pixel is made up of an InGaAs photodiode and a ROIC electrically connected by an
indium bump. A timing generator in the ROIC provides an analog video output and AD-TRIG output which are easily ob-
tained by just supplying a master clock (MCLK) and master start pulse (MSP) from external digital inputs.
The G12460-0606S has 64×64 pixels arrayed at a 50 μm pitch and their signals are read out from a single video line. Light
incident on the InGaAs photodiodes is converted into electrical signals which are then input to the ROIC through indium
bumps. Electrical signals in the ROIC are converted into voltage signals by charge amplifiers and then sequentially output
from the video line by the shift register. The G12460-0606S is hermetically sealed in a TO-8 package together with a one-
stage thermoelectric cooler to deliver low-cost yet highly stable operation.
Features
Spectral response range: 1.12 to 1.9 μm
Excellent linearity by offset compensation
High sensitivity: 1600 nV/e-
Simultaneous charge integration for all pixels
(global shutter mode)
Simple operation (built-in timing generator)
One-stage TE-cooled
Low cost
Applications
Thermal imaging monitor
Laser beam profiler
Near infrared image detection
Foreign object detection
Block diagram
A sequence of operation of the readout circuit is described below.
In the readout circuit, the charge amplifier output voltage is sampled Start
and held simultaneously at all pixels during the integration time deter-
mined by the low period of the master start pulse (MSP) which is as a
frame scan signal. Then the pixels are scanned and their video signals
are output.
Pixel scanning starts from the starting point at the upper left in the
right figure. The vertical shift register scans from top to bottom in the
right figure while sequentially selecting each row.
For each pixel on the selected row, the following operations are per-
formed:
 Transfers the sampled and held optical signal information to the sig-
nal processing circuit as a signal voltage.
 Resets the amplifier in each pixel after having transferred the signal
voltage and transfers the reset voltage to the signal processing circuit.
‘ The signal processing circuit samples and holds the signal voltage 
and reset voltage .
’ The horizontal shift register scans from left to right in the right fig-
ure, and the voltage difference between  and  is calculated in the
offset compensation circuit. This eliminates the amplifier offset volt-
age in each pixel. The voltage difference between  and  is output
as the output signal in the form of serial data.
The vertical shift register then selects the next row and repeats the
operations from  to ’. After the vertical shift register advances to the
64th row, the MSP, which is a frame scan signal, goes high. After that,
when the MSP goes high and then low, the reset switches for all pixels
are simultaneously released and the next frame integration begins.
64 × 64 pixels
Signal processing circuit
Shift register
www.hamamatsu.com
End
Offset
compensation
circuit
VIDEO
KMIRC0043EA
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