GSC24BC01 Datasheet, PDF (4/9 Pages) GTM CORPORATION – 2-WIRE SERIAL EEPROMS

ISSUED DATE :2006/06/14
REVISED DATE :
AC Characteristics Applicable over recommended operating range from: TA=-40 ~ +85к,
VCC=+1.8 ~ 5.5V, CL=1 TTL Gate & 100pF (unless otherwise noted)
Parameter
Symbol
Test Condition
Min TYP Max
Clock Frequency, SCL
Clock Pulse Width Low
fSCL
tLOW
VCC=1.8V
VCC=2.7 ~ 5.5V
VCC=1.8V
VCC=2.7 ~ 5.5V
-
-
100
400
4.7
1.2
-
-
Clock Pulse Width High
Noise Suppression Time (1)
tHIGH
tI
VCC=1.8V
VCC=2.7 ~ 5.5V
VCC=1.8V
VCC=2.7 ~ 5.5V
4.0
0.6
-
-
-
-
100
50
Clock Low to Data Out Valid
tAA
VCC=1.8V
VCC=2.7 ~ 5.5V
0.1
0.1
-
4.5
0.9
Time the bus must be free before
a new transmission can start (1)
tBUF
VCC=1.8V
VCC=2.7 ~ 5.5V
4.7
1.2
-
-
Start Hold Time
tHD.STA
VCC=1.8V
VCC=2.7 ~ 5.5V
4.0
0.6
-
-
Start Setup Time
Data in Hold Time
tSU.STA
tHD.DAT
VCC=1.8V
VCC=2.7 ~ 5.5V
VCC=1.8V
VCC=2.7 ~ 5.5V
4.7
0.6
-
-
0
0
-
-
Data in Setup Time
Input Rise Time (1)
tUS.DAT
tR
VCC=1.8V
VCC=2.7 ~ 5.5V
VCC=1.8V
VCC=2.7 ~ 5.5V
200
100
-
-
-
-
1.0
0.3
Input Fall Time (1)
tF
VCC=1.8V
VCC=2.7 ~ 5.5V
-
-
300
300
Stop Setup Time
Data Out Hold Time
tSU.STO
tDH
VCC=1.8V
VCC=2.7 ~ 5.5V
VCC=1.8V
VCC=2.7 ~ 5.5V
4.7
0.6
-
-
100
50
-
-
Write Cycle Time
5.0V, 25к, Byte Mode
tWR
VCC=1.8V
VCC=2.7 ~ 5.5V
Endurance ^VCC=1.8V
(1) VCC=2.7 ~ 5.5V
-
-
5
5
1M
1M
-
-
Note: 1. This parameter is characterized and not 100% tested.
Unit
KHz
s
s
ns
s
s
s
s
s
ns
s
ns
s
ns
ms
Write
Cycles
Device Operation
Clock and Data Transitions: Transitions on the SDA pin should only occur when SCL is low (refer to the Data
Validity timing diagram in Figure 5). If the SDA pin changes when SCL is high, then the transition will be
interpreted as a START or STOP condition.
START Condition: A START condition occurs when the SDA transitions form high to low when SCL is high.
The START signal is usually used to initiate a command (refer to the Start and Stop Definition timing diagram in
Figure 6).
STOP Condition: A STOP condition occurs when the SDA transitions form low to high when SCL is high (refer
to Figure 6. START and STOP Definition timing diagram). The STOP command will put the device into standby
mode after no acknowledgment is issued during the read sequence.
Acknowledge: An acknowledgement is sent by pulling the SDA low to confirm that a word has been
successfully received. All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words, so acknowledgments are usually issued during the 9^th clock cycle.
Standby Mode: Standby mode is entered when the chip is initially powered-on or after a STOP command has
been issued and any internal operations have been completed. .
Memory Reset: In the event of unexpected power or connection loss, a START condition can be issued to
restart the input command sequence. If the device is currently in write cycle mode, this command will be
ignored.
GSC24BC01/02/02/04/08/16
Page: 4/9