GS8673EQ36BGK-550S Datasheet, PDF (9/25 Pages) GSI Technology – For use with GSI SRAM Port IP

GS8673EQ18/36BK-725S/625S/550S
Truth Table
SA
R
W
Current Operation
D
Q
↑CK
↑CK
↑CK
↑CK
↑KD
↑KD
↑CQ
↑CQ
(t_n)
(t_n+½)
(t_n)
(t_n)
(t_n)
(t_n)
(t_n+½)
(t_n+3)
(t_n+3½)
X
X
1
1
NOP
X
X
Hi-Z / 0
X
V
1
0
Write Only
D1
D2
Hi-Z / 0
V
X
0
1
Read Only
X
X
Q1
Q2
V
V
0
0
Read + Write
D1
D2
Q1
Q2
Notes:
1. 1 = High; 0 = Low; V = Valid (High or Low); X = Don’t Care.
2. D1 and D2 indicate the first and second pieces of write data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of read data transferred during Read operations.
4. When D ODT is disabled (MZT[1:0] = 00), Q pins are tri-stated for one cycle in response to NOP and Write Only commands, 3 cycles after
the command is sampled.
5. When D ODT is enabled (MZT[1:0] = 01 or 10), Q pins are driven Low for one cycle in response to NOP and Write Only commands, 3
cycles after the command is sampled.
Rev: 1.03 6/2014
9/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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