GS8673ED36BGK-675I Datasheet, PDF (9/31 Pages) GSI Technology – 72Mb SigmaQuad-IIIe, Burst of 4 ECCRAM

GS8673ED18/36BK-675/625/550/500
Functional Description
Separate I/O ECCRAMs, from a system architecture point of view, are attractive in applications that execute continuous
back-to-back alternating Reads and Writes. Therefore, the SigmaQuad-IIIe ECCRAM interface and truth table are optimized for
continuously alternating Reads and Writes. Separate I/O ECCRAMs are unpopular in applications where block transfers of Reads
or Writes are needed because half of the data pins will go unused during the block transfer, potentially cutting Separate I/O
ECCRAM data bandwidth in half. Applications of this sort are better served by Common I/O ECCRAMs such as the
SigmaDDR-IIIe series.
Truth Table
Previous
Operation
SA
R
W
Current
Operation
D
Q
(t_n–1)
↑CK ↑CK ↑CK
(t_n) (t_n) (t_n)
(t_n)
NOP
X11
NOP
↑KD ↑KD ↑KD ↑KD ↑CK ↑CK ↑CK
↑CK
(t_n+1) (t_n+1½) (t_n+2) (t_n+2½) (t_m) (t_m+180º) (t_m+1) (t_m+1+180º)
X
X
—
— Hi-Z/0 Hi-Z/0 —
—
Write
X1X
NOP
D3
D4
—
— Hi-Z/0 Hi-Z/0 —
—
Read
XX1
NOP
X
X
—
—
Q3
Q4
—
—
NOP
V10
Write
D1
D2
D3
D4 Hi-Z/0 Hi-Z/0
—
—
Read
VX0
Write
D1
D2
D3
D4
Q3
Q4
—
—
NOP
V0X
Read
X
X
—
—
Q1
Q2
Q3
Q4
Write
V0X
Read
D3
D4
—
—
Q1
Q2
Q3
Q4
Notes:
1. 1 = input High; 0 = input Low; V = input valid; X = input don’t care.
2. t_m= t_{n + RL}, where RL = Read Latency of the device.
3. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of Write Data transferred during Write operations.
4. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of Read Data transferred during Read operations.
5. When D input termination is disabled (MZT[1:0] = 00), Q drivers are disabled (i.e. Q pins are tri-stated) for one cycle in response to NOP and
Write commands, RL cycles after the command is sampled, except when preceded by a Read command.
6. When D input termination is enabled (MZT[1:0] = 01 or 10), Q drivers are enabled Low (i.e. Q pins are driven Low) for one cycle in response
to NOP and Write commands, RL cycles after the command is sampled, except when preceded by a Read command. This is done so the
Memory Controller can enable On-Die Termination on its data inputs without having to cope with the termination pulling tri-stated data inputs
to V_DDQ/2 (i.e., to the switch point of the data input receivers).
Rev: 1.06 5/2012
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology