GS8342DT07BGD-450 Datasheet, PDF (9/29 Pages) GSI Technology – 36Mb SigmaQuad-II+TM Burst of 4 SRAM

GS8342DT07/10/19/37BD-450/400/350/333/300
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
RW
Current
Operation
D
D
D
D
Q
Q
Q
K
(t_n-1)
Deselect
Write
Read
Deselect
Deselect
Read
K K K
(t_n) (t_n) (t_n)
X
1
1
X
1
X
X
X
1
V
1
0
V
0
X
V
X
0
K
(t_n)
Deselect
Deselect
Deselect
Write
Read
Write
K
(t_n+1)
X
D2
X
D0
X
D0
K
(t_n+1½)
X
D3
X
D1
X
D1
K
(t_n+2)
—
—
—
D2
—
D2
K
(t_n+2½)
—
—
—
D3
—
D3
K
(t_n+2)
Hi-Z
Hi-Z
Q2
Hi-Z
Q0
Q2
K
(t_n+2½)
Hi-Z
Hi-Z
Q3
Hi-Z
Q1
Q3
K
(t_n+3)
—
—
—
—
Q2
—
Write
V
0
X
Read
D2
D3
—
—
Q0
Q1
Q2
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Q
K
(t_n+3½)
—
—
—
—
Q3
—
Q3
Rev: 1.01a 8/2017
9/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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