GS8182D08BGD-400 Datasheet, PDF (9/36 Pages) GSI Technology – 18Mb SigmaQuad-IITM 18Mb SigmaQuad-IITM

GS8182D08/09/18/36BD-400/375/333/300/250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. Apply V_DD.
1b. Apply V_DDQ.
1c. Apply V_REF (may also be applied at the same time as V_DDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 ns to reset the DLL after
the clocks become stablized.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t_KCVar.)
• The DLL cannot operate at a frequency lower than that specified by the t_KHKH maximum specification for the desired
operating clock frequency.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
undefined errors or failures during the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Rev: 1.03d 11/2011
9/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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