GS81302D06E-450 Datasheet, PDF (9/31 Pages) GSI Technology – 144Mb SigmaQuad-II+ Burst of 4 SRAM

GS81302D06/11/20/38E-500/450/400/350
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
RW
Current
Operation
D
D
D
D
Q
Q
Q
Q
K
(t_n-1)
Deselect
KKK

(t_n) (t_n) (t_n)
X
1
1
K
(t_n)
Deselect
K
(t_n+1)
K
(t_n+1½)
K
(t_n+2)
K
(t_n+2½)
K
(t_n+2½)
X
X
—
—
Hi-Z
K
(t_n+3)
K
(t_n+3½)
K
(t_n+4)
Hi-Z
—
—
Write
X
1
X
Deselect
D2
D3
—
—
Hi-Z
Hi-Z
—
—
Read
X
X
1
Deselect
X
X
—
—
Q2
Q3
—
—
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
—
—
Deselect
V
0
X
Read
X
X
—
—
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
—
Write
V
0
X
Read
D2
D3
—
—
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Rev: 1.05c 8/2017
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology