GS8662DT19BD-450 Datasheet, PDF (8/28 Pages) GSI Technology – 72Mb SigmaQuad-II+TM Burst of 4 SRAM

GS8662DT07/10/19/37BD-450/400/350/333/300
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V_SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K,K)
input receivers. The input termination is always enabled, and the impedance is programmed via the same RQ resistor (connected
between the ZQ pin and V_SS) used to program output driver impedance, in conjuction with the ODT pin (6R). When the ODT pin
is tied Low, input termination is "strong" (i.e., low impedance), and is nominally equal to RQ*0.3 Thevenin-equivalent when RQ is
between 175Ω and 350Ω. When the ODT pin is tied High (or left floating—the pin has a small pull-up resistor), input termination
is "weak" (i.e., high impedance), and is nominally equal to RQ*0.6 Thevenin-equivalent when RQ is between 175Ω and 250Ω.
Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same
manner as for driver impedance (see above).
Note:
D, BW, K, K inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are
tri-stated, the input termination will pull the signal to V_DDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause
the receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result
in the device’s operating currents being higher.
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
RW
Current
Operation
D
D
D
D
Q
Q
Q
K
K K K
K
K
K
K
K
K
K
K
(t_n-1)
(t_n) (t_n) (t_n)
(t_n)
(t_n+1)
(t_n+1½)
(t_n+2)
(t_n+2½)
(t_n+2)
(t_n+2½) (t_n+3)
Deselect
X
1
1
Deselect
X
X
—
—
Hi-Z
Hi-Z
—
Write
X
1
X
Deselect
D2
D3
—
—
Hi-Z
Hi-Z
—
Read
X
X
1
Deselect
X
X
—
—
Q2
Q3
—
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
—
Deselect
V
0
X
Read
X
X
—
—
Q0
Q1
Q2
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
Write
V
0
X
Read
D2
D3
—
—
Q0
Q1
Q2
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Q
K
(t_n+3½)
—
—
—
—
Q3
—
Q3
Rev: 1.00b 8/2017
8/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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