GS82582TT19 Datasheet, PDF (8/26 Pages) GSI Technology – 288Mb SigmaDDR-II+TM Burst of 2 SRAM

GS82582TT19/37GE-450/400/375/333
Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table
DQ
K_n
LD
R/W
A+0
A+1
Operation

1
X
Hi-Z / *
Hi-Z / *
Deselect

0
0
D@K_n+1
D@K_n+1
Write

0
1
Q@K_n+2
Q@K_n+2
Read
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”.
2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP
and Write commands, 2.0 cycles after the command is sampled.
5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.0
cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the
state of the DQ input termination. See the Input Termination Impedance Control section for more information.
Burst of 2 Byte Write Clock Truth Table
BW
BW
Current Operation
K
K
K
(t_{n + 1})
(t_{n + 1½})
(t_n)
T
T
Write
Dx stored if BWn = 0 in both data transfers
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
F
F
Write Abort
No Dx stored in either data transfer
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
D
K
(t_{n +1} )
D1
D1
X
X
D
K
(t_{n + 1½})
D2
X
D2
X
Rev: 1.03 4/2016
8/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology